The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same which can simplify a process and reduce the manufacturing cost.
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. For example, the demand toward miniaturization has expedited the development of technologies for a package with a size approaching to that of a chip. The demand toward mounting reliability has highlighted the importance of packaging technologies for improving the efficiency of mounting work, and mechanical and electrical reliability after mounting.
As miniaturization and high performance are demanded in electric and electronic products, various technologies for providing a semiconductor package with high capacity have been researched and developed. A method for providing a semiconductor package of high capacity includes the high integration of a memory chip. Such high integration can be realized by integrating an increased number of cells in a limited space of a semiconductor chip.
However, high integration of a memory chip requires high precision technologies, such as a fine line width, and a lengthy development period. Under these situations, a stacking technology has been suggested as another method for providing a semiconductor package of high capacity. The stacking technology is divided into a method of embedding two stacked chips in one package, and a method of stacking two separate packages which are independently packaged.
In the conventional art, a stacked package is realized by attaching a first semiconductor chip in a face-down manner to a main substrate and attaching a second semiconductor chip in a face-up manner to the first semiconductor chip. Another way of packaging two semiconductor chips is to attach both first and second semiconductor chips in a face-up manner to a main substrate.
However, when two chips are stacked on bottom of each other, a problem is caused in that a difference is caused between the speeds of electrical signals transmitted from the main substrate to the first and second semiconductor chips. When stacking two chips face up on a substrate, a problem occurs because the first semiconductor chip and the second semiconductor chip require redistribution processes, the number of processes increases and the manufacture costs are highly incurred.